1. Field of the Invention
The present invention relates to a display device, and more particularly, to a liquid crystal display, a manufacturing method thereof, and a method for testing a liquid crystal display (LCD). Although the present invention is suitable for a wide scope of applications, it is particularly suitable to obtain flexibility in testing an LCD and prevent signal delay during the testing of the LCD.
2. Description of the Related Art
As the modern society changes into an information-oriented society, a liquid crystal display (LCD) device, which is one type of information display device, is receiving more attention. Cathode ray tubes (CRTs), which were widely used up until now, have many advantages in terms of performance and price, but they also have the disadvantages of large size, heavy weight and high power consumption. In contrast, LCDs have the advantages of miniaturization, lightweight, a slim profile, and low power consumption. Therefore, LCDs are drawing more attention as an alternative to CRTs that are capable of overcoming the disadvantages of the CRTs.
The fabrication of LCDs includes a process of manufacturing a lower substrate in which thin film transistors (TFTs) are formed, a process of manufacturing an upper substrate in which a color filter layer is formed, a cell process for attaching the lower substrate and the upper substrate as well as injecting liquid crystal (LC) into a space therebetween, a module process of assembling a printed circuit board (PCB) and the like for driving of the LCD, and an assembling process for assembling a backlight unit and optical sheets to the LCD.
A failure test processes are performed in each of the above processes. First, when the lower substrate having the TFTs therein is completed, an array test is performed to test for TFT failure, pixel pattern failure, and line opening failure. Then, a liquid crystal (LC) panel test process is performed to test whether there is a failure in the LC panel after attaching the upper and lower substrates. The LC panel test process is also called a cell test process.
The LC panel test process is for determining the presence of several malformations, such as defects in optical characteristics in the active region of the LC panel caused by a foreign substances or by variations in material thickness within the active region, point defects caused by TFT failure, and line defects caused by an opening failure in gate lines and/or data lines. The advantages and disadvantages of an auto probe (A/P) used for testing the LC panel according to the related art will now be described.
A first type of test that includes an A/P pin test can be performed by contacting needle pins to all of data pads and gate pads of the LC panel after the upper and lower substrates are attached to each other and a grinding process is completed. Since the A/P pin test applies signals to all of the data pads and the gate pads, which are contacted with the needle pins, there is an advantage in that the test can be performed by applying test signals in the same manner as real signals would be applied in the actual driving of the LCD. However, since the A/P pin test has needle pins that need to contact each of the pads, once a contact failure occurs at one of the pads by one of the needle pins, a line defect is falsely detected. Another disadvantage is that a jig of needle pins used for contacting all of data pads and gate pads of the LC panel has to be manufactured for each model of LC panel. Further, such a test requires two or more operators.
A second type of test that includes the combination of an A/P pin test and a vision test that allows the needle pins to contact each of the gate pads and the data pads, and then tests the point defect and the line defect using a macro/micro (MAC/MIC) test system so as to overcome a disadvantage of the A/P pin test. More specifically, the A/P pin test and the vision test have an advantage in that only one operator is required in comparison to the related art A/P pin test but still do not solve the problem of false line defect detections due to pin contact failure.
A third type of test that includes a shorting bar test and the vision test has been developed to solve the disadvantages of the A/P pin test and the vision test. The shorting bar test and the vision test combine all of the even and odd gate pads together as well as all of the even and odd data pads together using shorting bars, and applies test signals to each of the gate and data lines to test the LC panel. The shorting bar test and the vision test will be described below with reference to FIG. 1.
FIG. 1 is a schematic view of a test for an LC panel according to the related art. As shown in FIG. 1, the LC panel 10 on which a gate pad part 17 and a data pad part 16 are formed is moved by a moving unit of an A/P pin system to a test area in which a data driver 11 and a gate driver 12 are disposed. The data driver 11 has a plurality of data test probes 14 and the gate driver 12 has a plurality of gate test probes 15. The data test probe 14 includes a data tape carrier package (TCP) on which a data driver IC is mounted, and a plurality of needle pins for electrical contact with shorting bars formed in the data pad part 16. Similarly, the gate test probe 15 includes a gate TCP on which a gate driver IC is mounted, and a plurality of needle pins for electrical contact with shorting bars formed in the gate pad part 17. The needle pins formed in the data test probes 14 and the gate test probes 15 contact even and odd shorting bars formed along the edge of the LC panel 1 and apply drive signals and data signals to the shorting bars of the LC panel 10 so as to perform a failure test, such as a line defect test and a point defect test.
FIG. 2 is a schematic view of a pad structure in an LC panel for the LC panel test shown in FIG. 1. As shown in FIG. 2, the LC panel 10 having the upper substrate and the lower substrate attached to each other is roughly divided into a pad region 10a and an active region 10b. The active region 10b includes red (R), green (G), and blue (B) pixels formed in a matrix. The pad region 10a includes a data pad region 16 and a gate pad region 17 at sides thereof. The data pad region 16 includes data pads D1, D2, D3, D4, . . . extending to an edge of the pad region 10a for applying data signals to the R, G, and B pixels. The gate pad region 17 includes gate pads G1, G2, G3, . . . extending up to another edge of the pad region 10a for applying drive signals to the R, Q and B pixels.
For the shorting bar and vision tests, the pad region 10a includes an odd data shorting bar DS1 that connects to all of the odd data pads D1, D3, D5, . . . among the data pads D1, D2, D3, D4, D5, D6, . . . and an even data shorting bar DS2 that connects to all of the even data pads D2, D4, D6, . . . among the data pads D1, D2, D3, D4, D5, D6, . . . . Likewise, the pad region 10a also includes odd gate shorting bar GS1 that connects to all of the odd gate pads G1, G3, G5 . . . and even gate shorting bar GS2 that connects to all of the even gate pads G2, G4, G6, . . . . Shorting bar terminals of the gate shorting bars GS1 and GS2 and the data shorting bars DS1 and DS2 are formed at the opposite ends of the gate pad region 17 and at the opposite ends of the data pad region 16, respectively. As illustrated in FIG. 2, a cutting line 20 is used for electrically cutting the data shorting bars and the gate shorting bars DS1, DS2, GS1, and GS2 away from the data pads D1, D2, D3, . . . and the gate pads G1, G2, G3, . . . after the test. A process of performing the shorting bar and vision test will be described below using the LC panel 10 having the above structure.
Since the odd data shorting bar DS1 and the even data shorting bar DS2 connect all of data pads D1, D2, D3, . . . , the test is performed by having needle pins that only contact the terminals of the data shorting bars DS1 and DS2, unlike the related art A/P pin test. The shorting bars can be contacted at both ends for redundancy purposes. A test for a defective LC panel 10 is performed by applying data signals and drive signals to the shorting bars DS1, DS2, GS1, and GS2. The above test, which is similar to a test for the TFT array substrate, is a test in which the data pads and the gate pads are all grouped odd/even by the shorting bars and test signals are applied to all of the odd/even shorting bars with collective contact to all even/odd lines through respective even/odd shorting bars. Therefore, pin-contact failure is reduced as compared to the related art A/P pin test. Further, a separate jig is not required for each model of the LC panels because at most only 8 contacts, which can be spatially adjustable, are necessary.
The shorting bar and vision tests have the following problems. First, since the even/odd shorting bar test applies a signal to the shorting bar terminals disposed at opposite ends of the shorting bars during the test, a false line defect may be detected due to a signal delay to the central region of the LC panel. Second, since all of the lines are grouped as even/odd and the even pixels or odd pixels are tested collectively, the flexibility to be able to individually test each pixel or a small number of pixels is considerably deteriorated. That is, since signals are not applied to all of the pads to perform the test in the same manner as is done in the LCD driving of the related art A/P pin test, there are limitations in being able to accurately determining the locations and/or causes of failures.